(1) Field of the Invention
The present invention relates to a pointer processing apparatus, a POH terminating process apparatus, a method of POH terminating process and a pointer/POH terminating process apparatus in an SDH transmission system suitable for use in a pointer process and a Path-Overhead (POH) terminating process at the time of information transmission in a synchronous terminal network based on synchronous digital hierarchy (SDH) standardized by ITU-T (International Telecommunication Union-Telecommunication Sector).
With high-integrated and low power-consuming LSIs (large-scale integrated circuits) of these days, the development in a technique of semiconductor devices has been realizing various system levels of functions in one chip of an LSI. It is strongly demanded these years to decrease a size and a power consumption of a system (an SDH transmission apparatus) by inventing and configuring a hardware structure such that a scale of the hardware or a power consumption is decreased as much as possible and by equipping more functions on one chip of an LSI so as to configure the system (the SDH transmission system) with a small number of LSIs.
(2) Description of the Related Art
(A) Description of an outline of the SDH transmission system
SDH has been specified and standardized in order to unify interfaces for effectively multiplexing high-speed services and existing low-speed services in various countries in the world, as well known. In SDH, all transfer rates (bit rates) of data that should be transferred are unified to data transfer rates (155 Mbps×n: wherein n=1, 4, 16, 64) whose basic rate (multiplexing unit) is 155 Mbps (155.52 Mbps, to be exact) and the data is multiplexed, whereby various data including existing low-speed data (lower digital stage information) can be multiplexed. SDH can thereby flexibly cope with new services in the future.
In concrete, SDH employs a system in which a virtual “box” called a virtual container (VC) is defined, some pieces of lower digital stage information are accommodated in the “box” to be made higher digital stage information, and these “boxes” are collected and accommodated in a larger “box”, whereby various pieces of information having different transmission rates are finally accommodated in one large “box” and transmitted.
As shown in FIG. 148, for example, a basic multiplexing unit in SDH is called an STM-1 (Synchronous Transfer Mode Level 1) frame. The STM-1 frame accommodates one AU-4 to which an administrative unit pointer (AU (Administrative Unit) pointer) used to indicate an accommodation position of VC-4 described later and synchronize the frequency is added. Further, a frame of VC-4 accommodates 1 channel of data of 138 Mbps series called C (Container)-4 or 3 channels of TUG (Tributary Unit Group)-3.
Still further, in the frame of TUG-3, 1 channel of TU (Triburary Unit)-3 (34 Mbps series) or 7 channels of TUG-2 (6 Mbps series) are multiplexed, and in TUG-2, 1 channel of TU-2 or 3 channels of TU-12 are multiplexed. The above TU-3 is a frame formed in such a manner that a path overhead (POH: transfer destination information) is added to a frame of 34 Mbps series called C-3 to form VC-3 and a TU pointer used to indicate an accommodation position and synchronize the frequency is added to the VC-3.
TU-2 is a frame in which a POH is added to a frame of C-2 (6 Mbps series) to form VC-2 and a TU pointer is further added to the VC-2. TU-12 is a frame in which a POH is added to C-12 (2 Mbps series) to form VC-12 and a TU pointer is further added to the VC-12.
In one frame of an STM-1 signal, a maximum of 3 channels of TU-3, a maximum of 21 channels of TU-2 or a maximum of 63 channels of TU-12 can be multiplexed.
Now, a frame format of each of the above STM-1, TU-3, TU-3 and TU-12 will be described. Incidentally, the above TU-3, TU-2, TU-12 and the like will be hereinafter described simply as TU3, TU2, TU12 and so on.
(A-1) STM-1 Frame Format
FIG. 149 is a diagram showing a frame format of above STM-1. As shown in FIG. 149, an STM-1 frame has a two-dimensional byte array in 9 rows by 270 columns (bytes). Leading 9 rows by 9 columns consist of a section overhead (SOH) 231 and an AU (AU4) pointer 232. The following 9 rows by 261 columns are called a payload (SPE: Synchronous Payload Envelope) 233 used to accommodate multiplexed information.
The section overhead 231 consists of various operation maintenance information such as A1 and A2 bytes indicating a frame synchronization pattern of the STM-1 frame, B1 byte used to supervise a code error, etc. The AU4 pointer 232 consists of H1 bytes (H1#1-H1#3 bytes), H2 bytes (H2#1-H2#3 bytes) and H3 bytes (H3#1-H3#3 bytes) indicating an accommodation position (a leading address) of VC (VC4: refer to FIG. 150) in the payload 232.
Generally, an actual AU4 pointer value is stored in the above H1 bytes (H1#1 byte) and H2 bytes (H2#1 byte), and a fixed value is stored as concatenation pointer (CI: Concatenation Indication) in H2#2 byte, H2#2 byte, H2#2 byte and H2#2 byte.
As shown in FIG. 149, an offset pointer value indicating an address of a leading byte of VC4 is such defined that the 0th address starts after the H2#2 byte and the 782nd address ends before the H1#1 byte, for example. Accordingly, if the AU4 pointer value is “0”, it means that a frame phase of STM-1 coincides with that of VC4 so that the VC4 is continuously accommodated immediately after the H3 bytes (H2#2 byte).
If the AU4 pointer value is a value other than “0”, it means that a frame phase of STM-1 does not coincide with that of VC4 so that the VC4 is accommodated such that a leading byte (J1 byte) of the VC4 positions at an address shifted from the 0th address by a deviation of the phase as shown in FIG. 150, for example. Meanwhile, since an offset pointer value of AU4 is generally defined every three bytes, a frame phase of VC4 changes by 3 bytes if the pointer value changes by one.
The above H3 bytes (H3#1-H2#2 bytes) and 3 bytes following the H3 bytes are frequency adjusting bytes called negative stuff bytes and positive stuff bytes, respectively. If a minute difference exists between a clock frequency of the transmission frame (STM-1) and a clock frequency of the multiplexed information (VC4), these positive/negative stuff bytes are used (i.e., a stuff control is conducted) to adjust the frequency so as to absorb a difference in the clock frequency or a fluctuation in the phase of the transmission frame, thereby preventing lack of transferred information.
(A-2) TU3 Frame Format
FIG. 151 is a diagram showing a frame format of the above TU3. As shown in FIG. 151, a TU3 frame is expressed by a two-dimensional byte array in 9 rows by 86 columns (bytes). H1 bytes and H2 bytes in the leading 9 rows by 1 column are a TU (TU3) pointer used to indicate an accommodation position and synchronize a frequency of VC (VC3: refer to FIG. 152) in the payload 233. H3 bytes and 1 byte (an offset pointer value “0”) following the H3 bytes are negative stuff bytes and positive stuff bytes, respectively, used to adjust the frequency (frame phase). Meanwhile, a remaining part of 6 rows by 1 column other than the H1 through H3 bytes in the leading 9 rows by 1 column is fixed stuff bytes (Fixed Stuff).
As shown in FIG. 151, an offset pointer value showing an address of a leading byte of VC3 is such defined that the 0th address starts after the H3 byte and the 764th address ends before the H3 bytes.
Accordingly, if a TU3 pointer value is “0”, it means that a frame phase of TU3 coincides with that of VC3 so that the VC3 is continuously accommodated immediately after (the 0th address) the H3 bytes.
If the TU3 pointer value is a value other than “0”, it means that a frame phase of TU3 does not coincide with that of VC3 so that VC3 is successively accommodated such that a leading byte (J1 byte) of VC3 is positioned at an address shifted from the 0th address by a deviation of the phase as shown in FIG. 152, for example.
In FIG. 152, a part of 9 rows by 1 line including J1 byte indicated by a reference numeral 235 is called a path overhead of VC3 (VC3-POH), which is given at a point where a path and a defined VC3 path are assembled (multiplexing process), and retained up to a dimultiplexing point (dimultiplexing process) after information is transmitted. A state of code errors and the like in the transmitted information can be monitored end-to-end by monitoring the VC3-POH.
For this, the VC3-POH 235 has a format including, in addition to the above J1 byte, B3 byte, C2 byte, G1 byte, F2 byte, H4 byte and Z3 to Z5 bytes. A function of each of the above bytes is as below:                (1) J1 byte: called a path trace signal, used (monitored) to confirm on the receiving side whether a connection with a transmitting side normally continues or not (confirming connection of a path) by repeatedly transmitting a signal in a fixed pattern;        (2) B3 byte; used to monitor an error in a path, an operation result obtained through an operating process called BIP(Bip)8, which will be described later, being inserted as B3 byte of the next frame;        (3) C2 byte: a byte (a signal label) used to represent mapping configuration of VC3, at which various information such as UNEQ indication indicating that VC3 does not accommodate a payload, etc. is set, as will be described later;        (4) G1 byte: a byte used to show a status of a path, used for a function (FEBE) to send back a received result of monitoring an error in a path to the transmitting side of VC3 and a function of far end received failure (FERF) to send back a state of termination of the path to the transmitting side;        (5) F2 byte; a byte which can be freely used by a network operator in the case of a user channel;        (6) Z3 to Z5 bytes: bytes internationally reserved as spares;        According to an embodiment of this invention, J1 byte, B3 byte, C2 byte and G1 byte among the above bytes are monitored (terminated) in a POH terminating process which will be described later.        
(A-3) TU2 Frame Format
FIG. 153 is a diagram showing a frame format of the above TU2. As shown in FIG. 153, a TU2 frame has a two-dimensional byte array in 4 rows by 108 columns (bytes). V1 byte and V2 byte in the leading 4 rows by 1 column are a TU (TU2) pointer used to indicate an accommodation position and synchronize a frequency of VC2 (refer to FIG. 154). V3 byte and 1 byte following the V3 byte (to the right on the sheet) are a negative stuff byte and a positive stuff byte, respectively, used to adjust the frequency (frame phase). Incidentally, V4 byte is a byte internationally reserved to be used in the future.
As shown in FIG. 153, an offset pointer value showing an address of a leading byte of VC2 is such defined that the 0th address starts after V2 byte and the 427th address ends before V2 byte. Accordingly, if a TU2 pointer value is “0”, it means that a frame phase of TU2 coincides with that of the VC2 so that VC2 is continuously accommodated immediately after V2 byte (the 0th address), as well.
If the TU2 pointer value is a value other than “0”, it means that a frame phase of TU2 does not coincide with that of VC2 so that VC2 is accommodated such that a leading byte (V5 byte) of VC2 is positioned at an address shifted from the 0th address by a deviation of the phase as shown in FIG. 154, for example.
In FIG. 154, a part of 4 rows by 1 column including V5 byte indicated by a reference numeral 236 is called a path overhead of VC2 (VC2-POH). By monitoring the VC2-POH 236, it is possible to monitor a state of a code error, etc. of transmitted information of VC2 end-to-end.
For this, the VC2-POH 236 has a format including, in addition to the above-mentioned V5 byte, J2 byte, Z6 byte and Z7 byte. A function of each of the above bytes will be described later where a TU12 frame format is described since a path overhead of VC12 has the same format as the VC2-POH 236.
(A-4) TU12 Frame Format
FIG. 155 is a diagram showing a frame format of the above TU12. As shown in FIG. 155, a TU12 frame is expressed by a two-dimensional byte array in 4 rows by 36 columns (bytes). V1 byte and V2 byte in the leading 4 rows by 1 column are a TU (TU12) pointer used to indicate an accommodation position and synchronize a frequency of VC12 (refer to FIG. 156), similarly to the above TU2 frame format. V3 byte and 1 byte following the V3 byte are a negative stuff byte and a positive stuff byte, respectively, used to adjust the frequency (frame phase). Incidentally, V4 byte in TU12 is a spare byte internationally reserved to be used in the future.
As shown in FIG. 155, an offset pointer value showing an address of the leading byte of VC12 is such defined that the 0th address starts after V2 byte and the 139th address ends before V2 byte. Accordingly, if the TU12 pointer value is “0”, it means that a frame phase of TU12 coincides with that of VC12 so that the VC12 is continuously accommodated immediately after (the 0th address) V2 byte.
If the TU12 pointer value is a value other than “0”, it means that a frame phase of TU12 does not coincide with that of VC12 so that VC12 is accommodated such that a leading byte (V5 byte) of VC12 is positioned at an address shifted from the 0th address by a deviation of the phase as shown in FIG. 156, for example.
In FIG. 156, a part of 4 rows by 1 line (column) including V5 byte indicated by a reference numeral 237 is called a path overhead (VC12-POH) of VC12, which has a format including, similarly to VC2-POH 236, J2 byte, Z6 byte and Z7 byte, in addition to the above-mentioned V5 byte. A function of each of the above bytes is as below:                (1) V5 byte: a byte used for path-error monitoring on VC2 or VC12 through an operating process called BIP2, which will be described later, for FEBE used to send back to the transmitting side a notification as to whether there is received an error obtained through BIP2, for mapping configuration representation of VC2/VC12 by a signal label and for a far end received failure (FERF) of a path of VC2/VC12; namely, functions of B3, C2 and G1 bytes included in the above-mentioned VC3-POH 235 being assigned in one byte (8 bits) of V5 byte;        (2) J2 byte: a byte used as a path trace signal similarly to J1 byte included in the above-mentioned VC3-POH 235, used to confirm connection of a path;        (3) Z6 an Z7 bytes: spare bytes.        
In the embodiment of this invention, V5 byte and J2 byte among the above bytes are monitored (terminated) in the POH terminating process, which will be described later.
(A-5) AU4/TU3/TU2/TU12 Pointer Format
Pointer bytes of the above pointers (AU4/TU3/TU2/TU12 pointers) have the same format as shown in FIG. 157, which consists of NDF (New Data Flag) bits (N) of 4 bits, SS bits of 2 bits, a pointer value of 10 bits and a negative stuff byte.
Next, functions of the above DNF (New Data Flag) bits (N), the SS bits of 2 bits and the 10-bit pointer value will be described.                (1) NDF bits: showing two states below.                    NDF enable (“1001”)                        
This bit signal is used to immediately change an operation pointer value (an active pointer value) to a new pointer value. The NDF enable is detected when 3 bits or more of received pointer value coincide with the NDF bits “1001”. However, if the SS bits described later are not an appropriate value, the NDF enable is not detected, which leads to an invalid pointer.                NDF disable (“0110”)        
This bit signal is used to transfer a normal pointer value, which also includes increment/decrement (I/D) indication described later. If the SS bits are not an appropriate value, the pointer is made to be an invalid pointer.
If the NDF bits are in a state other than the above cases (neither NDF enable nor NDF disable), the pointer is made be an invalid pointer.                (2) SS bits: this bit signal shows a size of VC in AU/TU as shown in TABLE 1 below.        
TABLE 1correspondence between signal sizeand SS bit valuesignal sizeSS bit valueAU410TU310TU200TU1210                (3) 10 bit pointer value: this signal shows a leading position (an offset pointer value) of VC in AU/TU as a binary code. This value consists of increment (I) bits and decrement (D) bits each of which is of 5 bits. A valid range of the pointer value is determined according to each signal size as shown in TABLE 2 below.        
TABLE 2correspondence between signal sizeand valid pointer valuesignal sizeSS bit valueAU40-782TU30-764TU20-427TU120-139
The increment indication is valid when the operation pointer value and an inversion of the I bits are 3 bits or more and an inversion of the D bits is 2 bits or less. When the increment indication is effective, data in the positive stuff byte region (immediately after the H3/V3 byte) is not read. On the other hand, the decrement indication is valid when the operation pointer value and an inversion of the D bits are 3 bits or more and an inversion of the I bits is 2 bit or less. When the decrement indication is valid, data in the negative stuff byte region (the H3/V3 byte) is read.
When H1 and H2 bytes or V1 and V2 bytes are all “1”, the indication becomes PAIS (Path Alarm Indication Signal) indication.
FIG. 158 is a diagram for illustrating state transition of the pointer. As shown in FIG. 158, the pointer transits three states, i.e., a normal state (NORM), an abnormal state (LOP) and an alarm detection state (PAIS). In FIG. 158, “NDF” represents NDF enable detection, “NORx3” represents normal pointer value 3-frame consecutive coincidence detection, “INC/DEC” represents increment/decrement indication detection, “INVxN” represents N-frame consecutive invalid pointer detection, “NDFxN” represents N-frame consecutive NDF-enable detection, and “AISx3” represents 3-frame consecutive PAIS-indication detection.
If a normal pointer is consecutively detected three times (over three frames), the INC/DEC indication is detected or an NDF enable signal is detected once in the normal state, a state of the pointer remains in the normal state, as shown in FIG. 158. If an invalid pointer (INV) or an NDF enable signal is consecutively detected predetermined times, the state of the pointer becomes the LOP state. If AIS is received three times consecutively, the state of the pointer becomes the alarm detection (PAIS) state.
If AIS is consecutively detected three times in the LOP state, the state of the pointer transits to the alarm state. If the invalid pointer is consecutively detected predetermined times in the alarm state, the state of the pointer transits to the LOP state. In order to make the pointer transit from the LOP state to the normal state, it is only necessary to consecutively detect the normal pointer three times. In order to make the pointer transit from the alarm state to the normal state, it is only necessary to detect the normal pointer three times successively or detect the NDF enable signal once.
(B) Description of an SDH Transmission Network
FIG. 159 is a block diagram showing an example of an SDH transmission network. In FIG. 159, reference numeral 301 denotes a subscriber terminal, 302 denotes a network terminating apparatus (NT), 303 and 306 denotes a line terminating apparatus (LT), 304 denotes a switching apparatus (SW), 305 denotes a multiplexing apparatus (MUX) and 307 denotes a relay transmission line.
In the SDH network shown in FIG. 159, data from plural subscriber terminals 301 (or a repeater) is assembled into an STM-n frame (where n=1, 4, 16, 64) by the multiplexing apparatus 305, undergone an overhead (SOH, POH) terminating/changing process and an AU/TU pointer terminating/changing process, etc. by the line terminating apparatus 306, then transmitted to an opposite side subscriber terminal 301 over the relay transmission line 307.
For this, the above line terminating apparatus 306 generally has an AU4 pointer processing unit 244′ and a TU pointer processing unit 245′ as a pointer processing apparatus 243 if paying an attention to a pointer processing part as shown in FIG. 160, for example. When considering the STM-1 frame as received multiplex data, a maximum of 3 channels in the case of TU3, a maximum of 21 channels in the case of TU2, or a maximum of 63 channels in the case of TU12 are multiplexed in the STM-1 frame as described before with reference to FIG. 148. Therefore, the TU pointer processing unit 245′ is, in general, provided with pointer detecting units 246, elastic store (ES) memory 247 for changing the TU pointer and pointer processing (inserting) units 248 equal in number to at least frames (channels) (a maximum of 63 channels) in the TU level accommodated in the STM-1 frame.
In the TU4 pointer processing unit 244′, reference numeral 244 denotes an AU4 pointer detecting unit and 245 denotes a serial/parallel (S/P) converting unit. Reference numeral 249 denotes a parallel/serial (P/S) converting unit.
The AU pointer detecting unit 244 detects (extracts) an AU4 pointer of received multiplex data (AU4 frame in which SOH of the STM-1 has been terminated) to conduct a terminating process on the AU4 pointer. The S/P converting unit 245 separates a VC4 signal in which the AU4 pointer has been terminated into frames (channels) in the TU level (TU3/TU2/TU12).
In the TU pointer processing unit 245′, each of the pointer detecting units 246 analyzes the received TU pointer and detects a state of the received TU pointer. Each of the ES memory 247 transfers the data clocks from a clock on the transmission line's side to a clock on the apparatus's side. Each of the pointer processing units 248 conducts a process to calculate a pointer, insert the pointer and the like on data read out from the corresponding ES memory 247. The P/S converting unit 249 multiplexes separated data of each channel.
With the above structure, the above pointer processing apparatus 243 conducts a process on frames in the TU level multiplexed in the STM-1 frame (VC4 frame) for each channel. Namely, the S/P converting unit 245 conducts S/P conversion on data in the TU level multiplexed in the STM-1 frame to separate the data into channels, then the corresponding pointer detecting unit 246 detects (extracts) a TU pointer from each of the separated data.
The extracted data (TU pointer) on each channel is temporarily written in the corresponding ES memory 247 according to a clock on the transmission line's side, then read out according to a clock on the apparatus's side so as to transfer the clocks. After that, each data is undergone a pointer process according to a clock on the apparatus's side in the corresponding pointer processing unit 248, undergone P/S conversion by the P/S converting unit 249 to be multiplexed, then outputted as transmit multiplex data.
The pointer process conducted in each of the pointer processing units 248 signifies a process such as to analyze a received pointer, detect an alarm, update an operation pointer (an active pointer), change (transmit) a pointer, etc.
(C) Description of an Outline of the POH Terminating Process
In the SDH transmission system, there are generally set two lines, i.e., a working line and a stand-by line, between two line terminating apparatus 306. The receiving side confirms a quality of communicating lines, i.e., a working line and a stand-by line, to appropriately switch from the working line to the stand-by line according to a degree of degradation of the quality of the working line.
To this end, the line terminating apparatus 306 confirms a quality of the line on the basis of a frame format of a multiplex signal (assuming here an STM-1 frame) in the SDH transmission system and TU format signals of TU3, TU2, TU12 and the like multiplexed (mapped) in the STM-1 frame.
In concrete, the line terminating apparatus 306 conducts various POH terminating processes such as BIP (Bit Interleaved Parity) operation, etc. to monitor an error in the path on a POH in a signal of TU3, TU2 or TU12 multiplexed in the received STM-1 frame so as to detect degradation of the quality of the line, and generates a control signal used to switch a line for each of the formats of TU3, TU2 and TU12.
However, there are mapped a maximum of 3 channels in the case of TU3, a maximum of 21 channels in the case of TU2 or a maximum of 63 channels in the case of TU12 in an STM-1 frame as described above. It is therefore necessary to conduct the above POH terminating process a number of times equal to the number of channels corresponding to signal sizes of TU format signals, separately (in parallel).
For this, the line terminating apparatus 306, in general, detects a leading position of a VC-4 format from a pointer value in H1 and H2 bytes of the STM-1 frame, separates the TU format signals multiplexed in VC-4 on the basis of the detected leading position and multiplex setting information (mapping setting information) of TU3, TU2 and TU12, and conducts the POH terminating process in different circuits for respective TU channels, separately.
When signals multiplexed in a STM-1 frame are all TU12, it is necessary to conduct the POH terminating process 63 times for 63 channels in TU12. As a result, a maximum of 63 circuits for conducting the POH terminating process on 63 channels become necessary.
Next, an outline of the POH terminating process will be described.
(C1) J1 and J2 Byte Terminating Process
It is possible, as described above, to confirm connection of a path by monitoring J1 byte included in the VC3-POH 235, and J2 byte included in the VC2/VC12-POHs 236 and 237.
As shown in FIG. 161, for example, if POH (“A”) is added in an apparatus on the transmitting side “#1” and POH (“B”) is added as a correct line setting in an apparatus on the transmitting side “#2”, an apparatus on the receiving side “#3” terminates received POHs (“A” and “B”) so as to monitor J1 byte and J2 byte.
In concrete, each of the above J1 and J2 bytes (path trace signal) is a signal obtained by adding a trace signal (name of a path) consisting of 15 ASCII characters to a path signal of VC3/VC2/VC12, which has a format shown in FIG. 162, for example, and is able to transfer 15 ASCII characters (ASCII data bit “X”) in a multiframe of 16 bytes.
So long as checking whether a received value (name of a receiving path) coincides with a reception expected value (name of a path that should be received) or not, the apparatus on the receiving side “#3” can confirm whether a received signal is connected to a proper apparatus or not. If not coincide, TIM (Trace Indicator Mismatch) representing that the received value does not coincide with the reception expected value is detected so that a mismatch alarm is generated.
In the frame format of a path trace signal shown in FIG. 162, the MSBs (the most significant bits) of 16 frames (totaling 16 bits) are called a multiframe indicator. By detecting the multiframe indicator (“1000 0000 0000 0000”), a path trace signal is detected. The multiframe indicator is used to detect out-of-synchronization (LOM: Loss Of Multiframe). Detection of out-of-synchronization in seven stages forward and three stages backward is conducted under conditions below:                frame disagreement detection condition: a frame indicate pattern of 16 bits in a received signal is not “1000 0000 0000 0000” when the 16th byte of the multiframe is processed;        frame agreement detection condition: the frame indicate pattern of 16 bits in a received signal is “1000 0000 0000 0000” when the 16th byte of the multiframe is processed.        
In FIG. 162, bits “C” excepting the MSB in a frame numbered “0” are called CRC (Cyclic Redundancy Check)-7 parity bits, which is used in a CRC-7 operation using a generating polynomial X7+X3+1.
As shown in FIG. 163, for example, the receiving side conducts the CRC-7 operation on received data of “0”, to “15” (bit 1 to 8) with received data in a frame numbered “0” (path trace data) as 80 (HEX), compares a result of the operation with received CRC bits in a frame numbered “0” of the next multiframe to detect a CRC error. Incidentally, CRC error detection is conducted in three stages forward and in three stages backward, here.
(C2) B3 Byte Terminating Process
It is possible to detect an error (code error) in a path of VC3 signals by terminating B3 byte (as to its format, refer to FIG. 164) included in the VC3-POH 235 using an error parity system called BIP8 (Bit Interleaved Parity-8) operation. In this case, even parity is applied as the error parity system.
In concrete, BIP8 operation is a technique in which parity calculation is carried out on every 8 bits of counted data (in units of byte) to count parity of the same digits of one byte as a unit as shown in FIG. 165(a), for example, and a result of the counting is indicated at the same digit of BIP8 as shown in FIG. 165(b).
For instance, the receiving side carries out the parity calculation on each byte (8 bits) of data of 1 frame (85 bytes×9=765 bytes) of a VC3 signal, compares a result of the calculation with B3 byte extracted from the next frame to detect a parity error in each of bits from the MSB to the LSB (the least significant bit), as shown in FIG. 168. When a parity error is detected in a frame, 1 alarm is generated.
(C3) C2 Byte Terminating Process
It is possible to recognize a mapping configuration of a VC signal by terminating (monitoring a signal label) C2 byte (refer to FIG. 167) included in the VC3-POH 235 so that disagreement (mismatch) of a signal label (SLM) or UNEQ (representing that a VC3 signal does not accommodate a payload).
As C2 byte (signal label), a value (a mapping code of 8 bits) set according to a mapping configuration of a VC3 signal is defined as shown in FIG. 168, for example. When the VC3 signal does not accommodate a payload, ALL “0” which represents UNEQ is set.
The receiving side monitors C2 byte. When consecutively detecting C2 byte indicating UNEQ (ALL “0”) over 4 frames, the receiving side generates a UNEQ detection alarm. When detecting C2 byte with indication excepting UNEQ over 6 frames, the receiving side cancels the UNEQ detection alarm.
At this time, the receiving side compares a reception expected value of C2 byte set by a supervisor (maintenance engineer) with an actually received value of C2 byte to detect SLM. For instance, when disagreement between a received value and a reception expected value is consecutively detected 7 times, an SLM detection alarm is generated. When agreement is consecutively detected three times, the SLM detection alarm is cancelled.
(C4) G1 Byte Terminating Process
It is possible to recognize a state of a path of a VC3 signal by terminating G1 byte included in the VC3-POH 235. G1 byte has a format shown in FIG. 169, for example. High-order 4 bits of G1 byte (8 bits) are assigned as FEBE (Far End Block Error) bits [refer to {circle around (1)} in FIG. 169], and the following 1 bit is assigned as an FERF (Far End Receive Failure) bit [refer to {circle around (2)} in FIG. 169]. Incidentally, the remaining 3 bits [refer to {circle around (3)} in FIG. 169] are not presently used.
FEBE bits are used to return the number of parity error bits to the opposite apparatus (transmitting side) when a B3 (B1P8) parity error is detected in a received VC3 signal. As shown in FIG. 170, for example, the number of times of error detection obtained in the B3 byte terminating process is set as an EFBE error detection number. As shown in FIG. 170, states of 8 kinds are presently defined out of states (of 16 kinds) which can be indicated with 4 bits.
FERF bit is used to notify that a failure occurs in an apparatus on the receiving side which terminates the VC3 signal to an opposite apparatus, in which “0” represents a normal state, whereas “1” represents “VC3 Far End Receive Failure” notification state.
The receiving side monitors G1 byte to detect the number of errors in the opposite apparatus when a received code of the high-order 4 bits (FEBE bits) are other than “0000”, and counts them as 1 alarm. When the FERF bit is “1” is detected, the receiving side recognizes it as an FERF alarm. In this case, when the FERF bit is “1” is consecutively detected over 10 frames, an FERF alarm is generated. When the FERF bit of “0” is consecutively detected over 10 frames, the RERF alarm is cancelled.
(C5) V5 Byte Terminating Process
V5 byte included in the VC2-POH 236 or the VC12-POH 237 has a format shown in FIG. 171, for example. In V5 byte, high-order 2 bits are assigned as BIP2 bits ([refer to {circle around (1)} in FIG. 171], the following 1 bit is assigned as an FEBE bit [refer to {circle around (2)} in FIG. 171], the further following 1 bit is assigned as an RFI bit [refer to {circle around (3)} in FIG. 171] of V5 byte used to notify to a microcomputer, the still further following 3 bits are assigned as a signal label [refer to {circle around (4)} in FIG. 171] and the LSB 1 bit is assigned as an FERF bit [refer to {circle around (5)} in FIG. 171].
Therefore, the receiving side can detect an error (code error) on a path of a VC2/VC12 signal through BIP2 operation, a mapping configuration of the VC2/VC12 signal from a signal label, a status of the path of the VC2/VC12 signal from FERF bit, etc. by terminating V5 byte.
In the above BIP2 operation, even parity is applied in the error parity system similarly to the BIP8 operation on B3 byte described before. The BIP2 operation employs a technique in which parity calculation is carried out every other bit of counted data (of each byte) as shown in FIG. 172(a), for example. For this, parity is counted in even bits and odd bits in one byte, and a result of the counting is indicated at the high-order 2 bits of V5 byte as shown in FIG. 172(b).
The receiving side carries out parity calculation on every 2 bits in a region of the counted data of one multiframe of the VC2/VC12 signal as shown by a meshed region in FIG. 173, compares a result of the calculation with BIP2 bits of V5 byte extracted from the next multiframe to detect a parity error with both bits of the MSB and LSB. When a parity error (a maximum of 2 bits) is detected in 1 multiframe, 1 alarm is generated.
When the receiving side detects a V5 (BIP2) parity error of received VC2/VC12, the number of parity error bits (the number of detected errors in V5 byte) is set as FEBE as shown in FIG. 174, and return to an opposite apparatus. FEBE bit of V5 byte can represent two kinds of states with one bit at present so that it is defined that “1” is always set when the number of detected errors in V5 byte is “2” or more. As a signal label of the above-mentioned V5 byte, a value [mapping codes of 3 bits (bit number B5 to B7)] set according to a mapping configuration of the VC2/VC12 signal is defined as shown in FIG. 175, for example. As a signal label, ALL “0” representing UNEQ is set when the VC2/VC12 signal does not accommodate a payload, similarly to C2 byte included in the VC3-POH 235.
The receiving side monitors the signal label. When consecutively detecting V5 byte in which the signal label indicates UNEQ (ALL “0”) over 4 frames, for example, the receiving side generates a UNEQ detection alarm. When consecutively detecting V5 byte in which the signal label is other than UNEQ over 5 frames, the receiving side cancels the UNEQ detection alarm.
At this time, the receiving side compares a reception expected value of a signal label set by a supervisor with an actually received value of the signal label. When consecutively detecting disagreement of the signal label seven times, the receiving side generates a mismatch (SLM) detection alarm. When consecutively detecting agreement of the signal label three times, the receiving side cancels the SLM detection alarm.
The FERF bit is used to notify that a failure occurs in an apparatus on the receiving side which terminates a VC2/VC12 signal to an opposite apparatus, in which “0” represents a normal state, whereas “1” represents a “VC2/VC12 Far End Receive Failure notification state.
The receiving side monitors the FERF bit of V5 byte. When the FERF bit is “1” is detected, the receiving side recognizes FERF alarm. In this case, when consecutively detected FERF bit is “1” over 10 frames, the receiving side generates an RERF alarm. When consecutively detected FERF bit is “0” over 10 frames, the receiving side cancels the FERF alarm.
(C6) Performance Monitor (PM) Function
Performance monitor function is a function used for a line quality monitoring and maintenance of a transmission line in service. The number of detected parity errors (BIP8 and BIP2) and FEBE errors is counted in a cycle of a PM reset pulse fed from a microcomputer, and a result of the counting is notified to the microcomputer, as will be described later.
FIGS. 176(a) through 176(f) show an example of a performance monitoring operation on BIP errors. FIGS. 2177(a) through 177(g) show an example of the performance monitoring operation on FEBE errors.
The above pointer processing apparatus 243, however, conducts in parallel the pointer process for each channel (for each of different signal sizes accommodated in the STM-1 frame) on the STM-1 frame (multiplexed data). For this, the pointer processing apparatus 243 has the pointer detecting units 246, the ES memory 247, the pointer processing units 248, etc. equal in number to a maximum of 63 channels. This causes a large increase of a circuit scale, a power consumption, the number of circuits (wirings), etc. of the apparatus.
In the above pointer processing apparatus 243, the data clock is transferred from a clock on the transmission line's side to a clock on the apparatus's side in each of the ES memory 247 for changing the TU pointer. This causes a demand for a larger number of stages of the ES memory 247 in order to absorb affections of jitter and wander of the clock on the transmission line's side and the clock on the apparatus's side, which also leads to a large increase of a circuit scale, power consumption, the number of distributions, etc. in the apparatus.
Further, in the above pointer processing apparatus 243, a process on the AU4 pointer (a pointer changing process, in concrete) and a process on the TU pointer are separately conducted by different hardware. When a signal in the VC4 level and a signal in the VC3/VC2/VC12 level are cross-connected, it is necessary to provide different hardware such as a cross-connecting unit 224 for cross-connecting (TSI: Time Slot Interchange) each signal in the VC4 level and a cross-connect unit 225 for cross-connecting each signal in the VC3/VC2/VC12 level, which also leads to an increase of a scale of the line terminating apparatus 306.
Still further, the above SDH transmission technique, a TU format signal is separated from an STM-1 frame, and the POH terminating process is conducted on each of the TU format signal in parallel. For this, it is necessary to provide a maximum of 63 POH terminating process apparatus having the same structure corresponding to 63 channels in the line terminating apparatus 306, which also causes a large increase of a scale and a power consumption of the apparatus.